1. Field of the Invention
The invention relates to a semiconductor device, and more particularly to a semiconductor device having high-resistance metal layer embedded within an interlayer dielectric (ILD) layer.
2. Description of the Prior Art
With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate.
However, integration of metal gate and thin film resistor still faces some issues in conventional FinFET fabrication, such as direct penetration of contact plugs through thin film resistor due to poor location of thin film resistor thereby affecting the performance of the resistor. Hence, how to improve the current FinFET fabrication and structure has become an important task in this field.